Title :
Oxygen implantation for improved CMOS latchup immunity
Author :
Ratanaphanyarat, S. ; Verdonckt, S.V. ; Wong, S.S. ; Drowley, C.I.
Author_Institution :
Cornell University, Ithaca, New York
Abstract :
Improvement in CMOS latchup immunity has been achieved through the application of oxygen implantation to create both a lifetime reduction layer and a potential barrier in the bulk of Si wafers. The effects of the implanted layer on the MOSFET´S and the parasitic bipolar transistors are discussed. The MOSFET´s are not affected by the oxygen implantation. The reduction in common base current gain is 50% for the lateral and 90% for the vertical parasitic bipolar transistors. As a consequence, the latchup immunity is greatly improved.
Keywords :
Annealing; Bipolar transistors; CMOS technology; Carrier confinement; Epitaxial layers; MOSFET circuits; Oxygen; Silicon; Substrates; Testing;
Conference_Titel :
Electron Devices Meeting, 1987 International
DOI :
10.1109/IEDM.1987.191538