DocumentCode
3557366
Title
Extended abstract: on the property-based verification in SoC design flow founded on transaction level modeling
Author
Bombieri, Nicola ; Fedeli, Andrea ; Fummi, Franco
Author_Institution
ST Microelectron., Italy
fYear
2005
fDate
11-14 July 2005
Firstpage
239
Lastpage
240
Abstract
In this paper we present the properties specification language (PSL) utilization in a system level verification flow for system on chip (SoC) designs, A compositional approach is proposed and two properties-based techniques are described and compared in terms of properties refinement effort and simulation speed delay.
Keywords
formal verification; logic design; logic testing; specification languages; system-on-chip; SoC design; properties specification language; system level verification flow; system on chip; transaction level modeling; Algorithm design and analysis; Delay; Hardware; Logic design; Mathematical model; Performance analysis; Protocols; Specification languages; System-on-a-chip; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Formal Methods and Models for Co-Design, 2005. MEMOCODE '05. Proceedings. Third ACM and IEEE International Conference on
Print_ISBN
0-7803-9227-2
Type
conf
DOI
10.1109/MEMCOD.2005.1487922
Filename
1487922
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