Extended abstract: an environment for design verification of smart card systems using attack simulation in SystemC

Author

Rothbart, K. ; Neffe, U. ; Steger, Ch. ; Weiss, R. ; Rieger, E. ; Muehlberger, A.

Author_Institution

Graz Univ. of Technol., Austria

fYear

2005

fDate

11-14 July 2005

Firstpage

253

Lastpage

254

Abstract

In this paper an environment for design verification of smart cards using security attack simulation in SystemC is presented. The method for automatic instrumentation of the SystemC code is described, also depicted is the process by which design robustness against attacks is verified. This process involves the system behavior analysis using an extended control flow graph. The results discuss the system behavior analysis of a Java Card™ Virtual Machine.

Keywords

C language; Java; electronic design automation; fault simulation; formal verification; programming environments; smart cards; systems analysis; virtual machines; Java Card™ Virtual Machine; SystemC; automatic instrumentation; control flow graph; fault simulation; security attack simulation; smart card design verification; system behavior analysis; Automatic control; Control systems; Flow graphs; Instruments; Java; Process design; Robustness; Security; Smart cards; Virtual machining;

fLanguage

English

Publisher

ieee

Conference_Titel

Formal Methods and Models for Co-Design, 2005. MEMOCODE '05. Proceedings. Third ACM and IEEE International Conference on

Print_ISBN

0-7803-9227-2

Type

conf

DOI

10.1109/MEMCOD.2005.1487929

Filename

1487929