Extended abstract: polynomial model-based evaluation of the branch coverage metric for functional verification of hardware systems

As the latest version of the International Technology Roadmap for Semiconductor (ITRS) highlights, verification has become the dominant cost of the electronic system design process. Although advances in formal methods have improved some aspects of the task, software simulation remains the primary method of functional verification. Traditionally, heuristic coverage metrics have been used to evaluate the simulation-based verification process. This coverage-based approach has a very serious disadvantage: the metrics have no formal meaning and so there is no direct correlation between classes of bugs and coverage metrics. The main goal of this paper is to explore methods that provide a formal meaning to branch coverage with random test benches. The methods are based on polynomial models of the system under verification and they are independent of a particular fault model.