Title :
Impact of the back gate effect on bipolar junction transistors in smart power SOI technologies
Author :
Schwantes, Stefan ; Graf, Michael ; Dudek, Volker
Author_Institution :
ATMEL Germany, Heilbronn, Germany
Abstract :
This work investigates the effect of the back gate electrode on bipolar junction transistors (BJTs) in smart power SOI technologies. The impact on the BJT is discussed by means of measurements and device simulations. It is shown that proper back gate biasing results in a significant performance improvement for either the NPN or the PNP transistor. A design strategy is presented that offers an optimized utilization of the back gate effect.
Keywords :
circuit optimisation; circuit simulation; power bipolar transistors; silicon-on-insulator; NPN/PNP transistor; back gate effect; back gate electrode; bipolar junction transistors; design strategy; device simulations; smart power SOI technologies; Avalanche breakdown; Clamps; Electric breakdown; Electrodes; Impact ionization; Voltage;
Conference_Titel :
Power Semiconductor Devices and ICs, 2005. Proceedings. ISPSD '05. The 17th International Symposium on
Print_ISBN :
0-7803-8890-9
DOI :
10.1109/ISPSD.2005.1487962
