• DocumentCode
    3557419
  • Title

    PDP scan driver with NVDMOS and RESURF PLDMOS

  • Author

    Sun, Zhilin ; Sun, Weifeng ; Yi, Yangbo ; Chen, Chang ; Yao, Weilian ; Peng, Zhenxiong ; Shi, Longxing

  • Author_Institution
    National ASIC Syst. Eng. Res. Center, Southeast Univ., Nanjing, China
  • fYear
    2005
  • fDate
    23-26 May 2005
  • Firstpage
    151
  • Lastpage
    154
  • Abstract
    A high voltage CMOS IC technology by using 25μm thick epitaxy based on 1.2μm standard CMOS process has been developed. In this technology, LDMOS and VDMOS are fabricated together. Junction isolation is used to isolate VDMOS from LDMOS, low voltage CMOS, and other VDMOSs. Test results show that the rise time and the fall time of the output stage is about 45ns and 50ns, respectively. For the simplicity of the technology, the cost is saved.
  • Keywords
    CMOS integrated circuits; isolation technology; plasma displays; power MOSFET; power integrated circuits; 1.2 micron; 25 micron; 45 ns; 50 ns; CMOS IC technology; NVDMOS; PDP scan driver; RESURF PLDMOS; junction isolation; Annealing; CMOS process; CMOS technology; Costs; Epitaxial growth; Fabrication; Immune system; Isolation technology; Phosphors; Sun;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Power Semiconductor Devices and ICs, 2005. Proceedings. ISPSD '05. The 17th International Symposium on
  • Print_ISBN
    0-7803-8890-9
  • Type

    conf

  • DOI
    10.1109/ISPSD.2005.1487973
  • Filename
    1487973
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3557419