Low loss and small SiP for DC-DC converters

Author

Shiraishi, M. ; Iwasaki, T. ; Akiyama, N. ; Kawashima, T. ; Matsuura, N. ; Chiba, S.

Author_Institution

Hitachi Res. Lab., Ibaraki, Japan

fYear

2005

fDate

23-26 May 2005

Firstpage

175

Lastpage

178

Abstract

This paper presents a SiP (system in package) that integrates high-side and low-side MOSFETs and a driver IC. The developed SiP has been realized the smallest mount area and lowest loss of DC-DC converter compared with the conventional devices that have ever been reported. Low-inductance packaging technology and optimization of the MOSFETs and driver IC by the MCM method (MCM: mixed simulation of circuit and MOS-power-devices), reduce the mount area by 60% smaller and reduce the loss by 25% compared with conventional discrete devices, when Vin=12 V, Vout=1.3 V, Iout=25 A, f=1 MHz.

Keywords

DC-DC power convertors; circuit simulation; driver circuits; power MOSFET; semiconductor device packaging; 1 mHz; 1.3 V; 12 V; 25 A; DC-DC converters; MCM method; MOS-power-devices; MOSFET; SiP; driver IC; low-inductance packaging technology; system in package; Circuit simulation; DC-DC power converters; Driver circuits; Feedback; Inductance; Integrated circuit packaging; MOSFETs; Optimization methods; Pulse width modulation; Schottky diodes;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 2005. Proceedings. ISPSD '05. The 17th International Symposium on

Print_ISBN

0-7803-8890-9

Type

conf

DOI

10.1109/ISPSD.2005.1487979

Filename

1487979