Title :
Novel low capacitance VDMOS device for switching and RF power amplification
Author :
Sapp, S. ; Thorup, P. ; Challa, A.
Author_Institution :
Fairchild Semicond., San Jose, CA, USA
Abstract :
In this paper the development of a novel low voltage PLANAR gate VDMOS device and process is presented. The device architecture was developed to reduce output capacitance while maintaining low on-state resistance for use in power switching applications and RF power amplification. The 80V device employs charge-balance techniques to minimize on-resistance and also considers how to reduce output capacitance to reduce switching loss.
Keywords :
power MOSFET; power amplifiers; radiofrequency amplifiers; 80 V; PLANAR gate VDMOS device; RF power amplification; charge-balance technique; on-state resistance; output capacitance; power switching; switching loss; Bandwidth; Immune system; Low voltage; Parasitic capacitance; Permittivity; Power semiconductor switches; Power transistors; Radio frequency; Radiofrequency amplifiers; Silicon;
Conference_Titel :
Power Semiconductor Devices and ICs, 2005. Proceedings. ISPSD '05. The 17th International Symposium on
Print_ISBN :
0-7803-8890-9
DOI :
10.1109/ISPSD.2005.1487982
