DocumentCode
3557660
Title
High cell-efficiency synchronous MRAM adopting unified bit-line cache
Author
Kim, D.J. ; Ko, J.H. ; Cho, Chang Hyun ; Kang, D.W. ; Min, Kyou Sik ; Kim, Dong Myong ; Lee, S.J. ; Shin, H.S.
Author_Institution
Sch. of Electr. Eng., Kookmin Univ., Seoul, South Korea
Volume
39
Issue
16
fYear
2003
Firstpage
1166
Lastpage
1167
Abstract
Unlike the 1T1C cell of the DRAM that suffers the crucial limitation on the bit-line capacitance, the stored information in the couple of the magnetic-tunnel-junction (MTJ) cell is not related to the bit-line capacitance. To achieve the high cell efficiency for the synchronous magneto-resistive random access memory (MRAM), the unified bit-line cache scheme is proposed. It simplifies the column path and provides the low-latency column operations.
Keywords
cache storage; magnetoresistive devices; random-access storage; tunnelling magnetoresistance; high cell-efficiency MRAM; high-speed column operation; low-latency column operations; magnetic-tunnel junction cell; random access memory; synchronous magnetoresistive RAM; unified bit-line cache;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20030783
Filename
1226558
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