A study of electrical characteristics and reliability on flash EEPROM cell

In this paper, we analyzed the operation of flash EEPROM cell. ATHENA which is process simulator of SILVACO is used to make stacked gate flash memory cell structure, and also analyzed electrical characteristics of write/erase operations as in basic operations. We have studied on the optimum doping concentration of the floating gate to suppress the overerase problem in the Flash EEPROM´s. We analyzed gate oxide thickness and gate channel length how to effect in Vth, and then if Tox to be a shorter, Vth will decrease. This phenomenon is important to approve programming speed. As gate channel length is shorter and shorter, Vth decreases severely. Because Vth is effected by DIBL. The leakage current of non-selected cells with source bias 0(V) is high, but if small positive voltage is applied to source bias, the subthreshold current decreases rapidly. And N-type MOSFETs with various doping concentrations were fabricated and their electrical characteristics were analyzed. The results showed that a overerase problem can be prevented if the doping concentration of the floating gate is low enough