DRAM plate electrode bias optimization for reducing leakage current in UV-O3 and O2 annealed CVD deposited Ta2O5 dielectric films

A new plate biasing scheme is described which allowed the use of 65% higher supply voltage without increasing the leakage current for the UV-O₃ and O₂ annealed chemical-vapor-deposited tantalum pentaoxide dielectric film capacitors in stacked DRAM cells. Dielectric leakage was reduced by biasing the capacitor plate electrode to a voltage lower than the conventionally used value of V_cc/2. Ta₂O₅ films with 3.9 nm effective gate oxide, 8.5 fF/μm² capacitance and <0.3 μA/cm² leakage at 100°C and 3.3 V supply are demonstrated.