Title :
Contact technology for high performance scalable BiCMOS on TFSOI
Author :
Racanelli, M. ; Huang, W.M. ; Kuehne, S. ; Foerstner, J. ; Wong, S. ; Hwang, B.Y.
Author_Institution :
Adv. Custom Technol., Motorola Inc., Mesa, AZ, USA
Abstract :
A selective W contact layer is deposited on both poly and silicon electrodes to realize scalable, high performance TFSOI BiCMOS. A unique double spacer integration results in high performance MOS and bipolar operation while providing adequate separation between poly and silicon electrodes to prevent sidewall leakage. Switching speed more than twice that of comparable bulk circuits is demonstrated. Limitations imposed by conventional silicon- and metal-diffusing self aligned silicides (Ti and Pt) are described. Pt silicide limits scaling of the spacer width while Ti silicide limits scaling of the silicon thickness. Selective W is shown capable of maintaining good device and circuit performance while not imposing such limitations.<>
Keywords :
BiCMOS integrated circuits; integrated circuit metallisation; large scale integration; silicon-on-insulator; tungsten; PtSi; TFSOI; TiSi/sub 2/; W; circuit performance; double spacer integration; metal-diffusing self aligned silicides; scalable BiCMOS; selective contact layer; spacer width; switching speed; thin-film silicon-on-insulator; BiCMOS integrated circuits; CMOS technology; Circuit optimization; Electrodes; Furnaces; Silicides; Silicon; Space technology; Substrates; Vents;
Journal_Title :
Electron Device Letters, IEEE
