Author :
Goldrian, G. ; Huth, T. ; Krill, B. ; Lauritsen, J. ; Schick, H. ; Ouda, I. ; Heybrock, Simon ; Hierl, D. ; Maurer, Tobias ; Meyer, Nils ; Schafer, Andreas ; Solbrig, S. ; Streuer, T. ; Wettig, Tilo ; Pleiter, Dirk ; Sulanke, K.-H. ; Winter, F. ; Simma, H
Abstract :
Application-driven computers for lattice gauge theory simulations have often been based on system-on-chip designs, but the development costs can be prohibitive for academic project budgets. An alternative approach uses compute nodes based on a commercial processor tightly coupled to a custom-designed network processor. Preliminary analysis shows that this solution offers good performance, but it also entails several challenges, including those arising from the processor´s multicore structure and from implementing the network processor on a field-programmable gate array.
Keywords :
field programmable gate arrays; gauge field theory; parallel machines; quantum chromodynamics; system-on-chip; cell broadband engine; field programmable gate array; lattice gauge theory; parallel computing; quantum chromodynamics; system-on-chip designs; Computational modeling; Computer applications; Computer networks; Computer simulation; Costs; Engines; Lattices; Parallel processing; Quantum computing; System-on-a-chip; Cell Broadband Engine; QCD; field-programmable gate array; lattice quantum chromodynamics; massively parallel computing; performance modeling; torus network;
