• DocumentCode
    3558965
  • Title

    A Unifying Approach for Weighted and Diminished-1 Modulo 2^n+1 Addition

  • Author

    Vergos, H.T. ; Efstathiou, C.

  • Author_Institution
    Dept. of Comput. Eng. & Inf., Univ. of Patras, Patras
  • Volume
    55
  • Issue
    10
  • fYear
    2008
  • Firstpage
    1041
  • Lastpage
    1045
  • Abstract
    In this paper, it is shown that every architecture proposed for modulo 2n+1 addition of operands that follow the diminished-1 representation can also be used in the design of modulo 2n+1 adders for operands that follow the weighted representation. This is achieved by the addition of a constant-time operator composed of a simplified carry-save adder stage. The experimental results indicate that many architectures already proposed for the diminished-1 case, lead to very efficient adders for weighted operands, under this unifying approach.
  • Keywords
    adders; carry logic; residue number systems; carry-save adder stage; constant-time operator; diminished-1 modulo 2n + 1 addition; unifying approach; Adders; Computer architecture; Digital arithmetic; Digital filters; Digital signal processing; Digital signal processors; Finite impulse response filter; Informatics; Signal design; Signal processing algorithms; Diminished-1 representation; modulo $2^{n}+1$ addition; residue arithmetic; residue number system;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-7747
  • Type

    jour

  • DOI
    10.1109/TCSII.2008.2001964
  • Filename
    4653509
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3558965