Analysis of the Flash ADC Bandwidth–Accuracy Tradeoff in Deep-Submicron CMOS Technologies

Efficient handling of the flash analog-to-digital converter (ADC) bandwidth-accuracy tradeoff is essential to minimizing its figure-of-merit. In this work, an expression that represents the bandwidth-accuracy tradeoff is devised, and the effect of technology scaling on this tradeoff is demonstrated. Based on the derived expression, the interpolating flash ADC is analyzed, and it is shown that the interpolating architecture attains a superior bandwidth-accuracy product compared with the full-flash architecture, especially in deep-submicron technologies. The gain in performance achieved when using interpolation is formulated and verified using simulations.