• DocumentCode
    3559116
  • Title

    An Efficient Unknown Blocking Scheme for Low Control Data Volume and High Observability

  • Author

    Wang, Seongmoon ; Wei, Wenlong

  • Author_Institution
    NEC Labs. America, Inc., Princeton, NJ
  • Volume
    27
  • Issue
    11
  • fYear
    2008
  • Firstpage
    2039
  • Lastpage
    2052
  • Abstract
    This paper presents an efficient method to block unknowns for temporal compactors. The proposed blocking logic can reduce data volume required to control the blocking logic and increase the number of scan cells that are observed by temporal compactors. Control patterns, which specify values required at the control signals of the blocking logic, are compressed by linear feedback shift register reseeding. In this paper, the blocking logic gates for some scan chains that do not capture unknowns are bypassed. Since all scan cells in these scan chains can be observed without specifying the corresponding bits in control patterns, more scan cells are observed while a smaller number of bits are required to be specified. The seed size is further reduced by reducing the numbers of specified bits in the densely specified control patterns. The proposed method can always achieve the same fault coverage that can be achieved by directly observing scan chains without any output compaction. Experiments with large industrial designs clearly demonstrate that the proposed method is scalable to large circuits. Hardware overhead for the proposed unknown blocking scheme is very low.
  • Keywords
    circuit complexity; circuit feedback; data compression; fault diagnosis; integrated circuit design; integrated circuit testing; logic design; logic gates; logic testing; shift registers; IC chip complexity; blocking logic; blocking logic gates; data volume reduction; fault coverage; large industrial designs; linear feedback shift register reseeding; observability aspects; scan cells; seed size reduction; semiconductor technology; temporal compactors; test data compression; unknown blocking scheme; Circuit faults; Circuit testing; Compaction; Hardware; Linear feedback control systems; Linear feedback shift registers; Logic gates; Observability; Size control; Test data compression; $n$-detection testing; Blocking unknowns; linear feedback shift register (LFSR) reseeding; test data compression; unknown values;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/TCAD.2008.2006093
  • Filename
    4655565