DocumentCode :
3559117
Title :
Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs
Author :
Lin, Chung-Wei ; Huang, Shih-Lun ; Hsu, Kai-Chi ; Lee, Meng-Xiang ; Chang, Yao-Wen
Author_Institution :
Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei
Volume :
27
Issue :
11
fYear :
2008
Firstpage :
2007
Lastpage :
2016
Abstract :
Given a set of pins and a set of obstacles on routing layers, a multilayer obstacle-avoiding rectilinear Steiner minimal tree (ML-OARSMT) connects these pins by rectilinear edges within layers and vias between layers and avoids running through any obstacle to construct a Steiner tree with a minimal total cost. The ML-OARSMT problem is very important for many very large scale integration designs with pins being located in multiple routing layers that contain numerous routing obstacles incurred from IP blocks, power networks, prerouted nets, etc. As a fundamental problem with extensive practical applications to routing and wirelength/congestion/timing estimations in early design stages, it is desired to develop an effective algorithm for the ML-OARSMT problem to facilitate the design flow. However, there is no existing work on this ML-OARSMT problem. In this paper, we first formulate the ML-OARSMT problem with rectangular obstacles and then identify key different properties of this problem from its single-layer counterpart. Based on the multilayer obstacle-avoiding spanning graph, we present the first algorithm to solve the ML-OARSMT problem. Our algorithm can guarantee an optimal solution for any two-pin net and many multiple-pin nets. Experiments show that our algorithm results in 33% smaller total costs on average than a construction-by-correction heuristic which is widely used for Steiner-tree construction in the recent literature.
Keywords :
VLSI; integrated circuit design; integrated circuit modelling; network topology; trees (mathematics); IP blocks; ML-OARSMT construction; VLSI designs; multilayer obstacle-avoiding rectilinear Steiner minimal tree; multiple routing layers; rectilinear edges; spanning graphs; very large scale integration designs; wirelength/congestion/timing estimations; Algorithm design and analysis; Costs; Delay; Nonhomogeneous media; Pins; Routing; Steiner trees; Timing; Tree graphs; Very large scale integration; Layout; Steiner tree; physical design; routing;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2008.2006095
Filename :
4655566
Link To Document :
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