Testing check bits at no cost in RAMs with on-chip ECC

The authors address the problem of testing the check bits in RAMs with on-chip ECC. A solution is proposed in which the check bits are tested in parallel with the testing of the information bits. The solution entails finding a class of parity-check matrices that have the property that all the check bits can be tested for pattern-sensitive faults while the information bits are being tested, without any increase in the length of the test sequence. Further, the parity-check matrices are such that there is no loss in error-correction capabilities, and there is no penalty in the worst-case delay of the error-correcting logic.