Title :
Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator
Author :
Perri, Stefania ; Corsonello, Pasquale
Author_Institution :
Dept. of Electron., Univ. of Calabria, Rende
Abstract :
This paper presents a new efficient architecture for the design of fast low-cost single-clock-cycle binary comparators. The proposed 64-bit circuit requires only 1051 transistors and, when implemented by using the ST 90-nm 1-V CMOS technology, it exhibits a running frequency higher than 4 GHz with an average power dissipation of only ~ 4 mW. Comparison with the fastest comparator known in the literature demonstrates that, at a parity of technology used, the novel architecture is ~ 12% faster and requires ~ 69% less transistors.
Keywords :
CMOS integrated circuits; clocks; comparators (circuits); transistors; ST CMOS technology; power dissipation; single-clock-cycle binary comparator; size 90 nm; transistors; voltage 1 V; CMOS process; CMOS technology; Circuits; Clocks; Digital arithmetic; Frequency; Logic; Power dissipation; Throughput; Very large scale integration; CMOS dynamic circuits; VLSI circuits; comparator; digital arithmetic;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2008.2008063
