Title :
Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs
Author :
Lin, Shao-Hung ; Liu, Shen-Iuan
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
Abstract :
Full-rate bang-bang phase detectors (BBPDs) and bang-bang frequency detectors (FDs) are presented for continuous-rate clock and data recovery (CDR) circuits. The proposed BBPDs have only six latches, so they save the power and area. Their symmetric architecture minimizes the clock skew caused by the nonsymmetric layout. The proposed unilateral FDs have a wide detectable frequency range. The theoretical analysis for the proposed FDs is given. Two continuous-rate CDR circuits using the proposed BBPDs and FDs have been fabricated in a 0.18-mum CMOS process. They recover the NRZ data of a 231-1 PRBS from 622 Mbps to 3.125 Gbps. All of the measured bit error rates are less than 10-12.
Keywords :
CMOS integrated circuits; clock and data recovery circuits; error statistics; phase detectors; CMOS process; bang-bang frequency detector; bit error rate; bit rate 3.125 Gbit/s; bit rate 622 Mbit/s; continuous-rate clock and data recovery circuit; full-rate bang-bang phase detector; size 0.18 mum; symmetric architecture; unilateral continuous-rate CDR; Bit error rate; CMOS process; Circuits; Clocks; Latches; Phase detection; Phase frequency detector; Phase locked loops; Space vector pulse width modulation; Timing; Bang-bang phase detector (BBPD); bit error rate (BER); clock and data recovery (CDR); frequency detector (FD); phase-locked loop (PLL);
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2008.2008055
