Title :
Defect Tolerance for Nanoscale Crossbar-Based Devices
Author :
Tehranipoor, Mohammad ; Rad, Reza M P
Author_Institution :
Univ. of Connecticut, Storrs, CT
Abstract :
The need for defect maps and per-chip placement and routing limits the efficiency of test and defect tolerance techniques in nanoscale crossbar-based devices. The authors propose a method using two simulation programs that circumvents these difficulties to find fault-free implementations of logic functions on defective crossbars.
Keywords :
circuit simulation; fault diagnosis; integrated circuit testing; logic circuits; nanoelectronics; defect maps; defect tolerance; logic functions; nanoscale crossbar-based devices; per-chip placement; routing limits; simulation programs; test efficiency; CMOS technology; Circuit faults; Fault tolerance; Logic devices; Logic functions; Logic testing; Nanobioscience; Nanoscale devices; Programmable logic arrays; Redundancy;
Journal_Title :
Design Test of Computers, IEEE
DOI :
10.1109/MDT.2008.162
