• DocumentCode
    3559295
  • Title

    A Systematic Approach to Memory Test Time Reduction

  • Author

    Yeh, Jen-Chieh ; Chen, Chao-Hsun ; Wu, Cheng-Wen ; Kuo, Shuo-Fen

  • Volume
    25
  • Issue
    6
  • fYear
    2008
  • Firstpage
    560
  • Lastpage
    570
  • Abstract
    This article describes a method for reducing overall memory test time without sacrificing fault coverage. Key to this method is a test time reduction tool that helps remove redundant test items from the test flow, merge existing test patterns, and develop efficient new test patterns.
  • Keywords
    integrated circuit testing; semiconductor storage; fault coverage; memory test time reduction; redundant test items; systematic approach; test flow; test patterns; Algorithm design and analysis; Automatic testing; Costs; Pattern analysis; Probes; Random access memory; Semiconductor device testing; Semiconductor memory; Statistical analysis; System testing;
  • fLanguage
    English
  • Journal_Title
    Design Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2008.152
  • Filename
    4702880
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3559295