• DocumentCode
    3559296
  • Title

    Multisynchronous and Fully Asynchronous NoCs for GALS Architectures

  • Author

    Sheibanyrad, Abbas ; Greiner, Alain ; Miro-Panades, Ivan

  • Volume
    25
  • Issue
    6
  • fYear
    2008
  • Firstpage
    572
  • Lastpage
    580
  • Abstract
    Networks on chips constitute a new design paradigm for communication infrastructures in large multiprocessor SoCs. NoCs can use the GALS technique to address the difficulty of distributing a synchronous clock signal on the entire chip area. This article describes two approaches to implementing a distributed NoC in a GALS environment.
  • Keywords
    asynchronous circuits; clocks; network-on-chip; GALS architecture; asynchronous NoC; multiprocessor SoC; multisynchronous NoC; network-on-chip; synchronous clock signal distribution; Access protocols; Bandwidth; Circuit topology; Clocks; Delay; Frequency synchronization; Integrated circuit interconnections; Laboratories; Metastasis; Network-on-a-chip;
  • fLanguage
    English
  • Journal_Title
    Design Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2008.167
  • Filename
    4702882
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3559296