FPGA-based fast image warping with data-parallelization schemes

In this paper, we present an FPGA-based fast image warping method by applying data parallelization schemes. The parallelization of accesses to pixels relieves not only latency problem of the warping, but also bandwidth requirements of off-chip memory. The LUT data parallelization scheme efficiently replaces parallel arithmetic operations with neither of increased memory size for LUT entries nor clock frequency. Two implementations with different characteristics prove the effectiveness and efficiency of the proposed method.