DocumentCode
3559750
Title
A Visual Tradeoff Space for Formal Verification and Validation Techniques
Author
Drusinsky, Doron ; Michael, James Bret ; Shing, Man-Tak
Author_Institution
Dept. of Comput. Sci., Naval Postgrad. Sch., Monterey, CA
Volume
2
Issue
4
fYear
2008
Firstpage
513
Lastpage
519
Abstract
Numerous techniques exist for conducting computer-assisted formal verification and validation. The cost associated with these techniques varies, depending on factors such as ease of use, the effort required to construct correct requirement specifications for complex real-world properties, and the effort associated with instrumentation of the software under test. Likewise, existing techniques differ in their ability to effectively cover the system under test and its associated requirements. To aid software engineers in selecting the appropriate technique for the formal verification or validation task at hand, we introduce a three-dimensional tradeoff space encompassing both cost and coverage.
Keywords
formal verification; program testing; complex real-world properties; computer-assisted formal verification; formal validation techniques; software engineers; three-dimensional tradeoff space; visual tradeoff space; Costs; Embedded software; Embedded system; Formal verification; Instruments; NIST; Runtime; Software safety; Software testing; System testing; Assertion checkers; formal methods; model checking; software verification and validation;
fLanguage
English
Journal_Title
Systems Journal, IEEE
Publisher
ieee
ISSN
1932-8184
Type
jour
DOI
10.1109/JSYST.2008.2009190
Filename
4711369
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