DocumentCode
356002
Title
Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits
Author
Pant, Pankaj ; Roy, Rabindra K. ; Chatterjee, Abhijit
Author_Institution
Georgia Inst. of Technol., Atlanta, GA, USA
Volume
1
fYear
1999
fDate
1999
Firstpage
26
Abstract
We demonstrate a novel algorithm for assigning the threshold voltage to the gates in a digital random logic CMOS circuit for a dual-threshold voltage process. The tradeoff between static and dynamic power consumption has been explored. When used along with device sizing and supply voltage reduction techniques for low power, the proposed algorithm can reduce the total power dissipation of the circuits by as much as 50%
Keywords
CMOS logic circuits; low-power electronics; algorithm; dual-threshold voltage process; low-power digital random logic CMOS circuit; total power dissipation; transistor sizing; CMOS digital integrated circuits; CMOS logic circuits; CMOS process; CMOS technology; Consumer electronics; Energy consumption; Logic devices; Power dissipation; Threshold voltage; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1999. 42nd Midwest Symposium on
Conference_Location
Las Cruces, NM
Print_ISBN
0-7803-5491-5
Type
conf
DOI
10.1109/MWSCAS.1999.867200
Filename
867200
Link To Document