Low-power binding of function units in high-level synthesis

This work considers binding of function units, operating at multiple voltages, in a post-scheduling scenario. The main aim is to minimize the power consumption due to switching activities on the physical adders and multipliers etc. To achieve this, switching activities on the function units are gathered through profiling the data-flow graph of the design by employing random input patterns. The problem of binding is then transformed into a graph-theory problem and solved for optimization of power consumption. Two approaches are considered in this work: a greedy approach, and an optimal approach. Cases are considered when all the resources are operating at the same voltage, as well as, when resources are operating at possibly different voltages