DocumentCode
356036
Title
A VLSI architecture for joint source-channel trellis coding
Author
Pérez, Luis González ; Boutillon, Emmanuel
Author_Institution
Ecole Nat. Superieure des Telecommun., Paris, France
Volume
1
fYear
1999
fDate
1999
Firstpage
223
Abstract
A VLSI architecture for a joint source and channel trellis coder is presented. For a noisy channel and low SNR, it can be more efficient to use a joint source and channel coding scheme than a tandem system where source and channel coders are designed separately. In the architecture presented in this paper, we show that the trade off complexity-performance, in terms of source distortion, outperforms the classical tandem scheme
Keywords
VLSI; channel coding; source coding; trellis codes; SNR; VLSI architecture; complexity-performance trade-off; joint source-channel trellis coding; noisy channel; source distortion; Channel capacity; Channel coding; Decoding; Delay; Error correction codes; Image reconstruction; Protection; Shift registers; Source coding; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1999. 42nd Midwest Symposium on
Conference_Location
Las Cruces, NM
Print_ISBN
0-7803-5491-5
Type
conf
DOI
10.1109/MWSCAS.1999.867248
Filename
867248
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