• DocumentCode
    3560600
  • Title

    Planar GeOI TFET Performance Improvement With Back Biasing

  • Author

    Matheu, Peter ; Ho, Byron ; Jacobson, Zachery A. ; Liu, Tsu-Jae King

  • Author_Institution
    Appl. Sci. & Technol. Grad. Program, Univ. of California, Berkeley, CA, USA
  • Volume
    59
  • Issue
    6
  • fYear
    2012
  • fDate
    6/1/2012 12:00:00 AM
  • Firstpage
    1629
  • Lastpage
    1635
  • Abstract
    Reverse back biasing of a planar germanium-on-insulator tunneling field-effect transistor provides for significant improvement in ION/IOFF, by over an order of magnitude for 0.25 V operating voltage. Optimization of the gate-to-source overlap and source doping gradient is key to maximizing the benefit of back biasing.
  • Keywords
    field effect transistors; germanium; back biasing; gate-to-source overlap; planar germanium-on-insulator tunneling field-effect transistor; source doping gradient; voltage 0.25 V; Doping; Electrodes; Junctions; Logic gates; MOSFET circuits; Silicon; Tunneling; Germanium-on-insulator (GeOI); reverse back bias; tunneling FET (TFET);
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • Conference_Location
    4/19/2012 12:00:00 AM
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2012.2191410
  • Filename
    6187725
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3560600