DocumentCode :
3560718
Title :
A 1300-V 0.34- \\Omega \\cdot\\hbox {cm}^{2} Partial SOI LDMOSFET With Novel Dual Charge Accumulation Layers
Author :
Elahipanah, Hossein ; Orouji, Ali A.
Author_Institution :
Dept. of Electr. Eng., Semnan Univ., Semnan, Iran
Volume :
57
Issue :
8
fYear :
2010
Firstpage :
1959
Lastpage :
1965
Abstract :
In this paper, for the first time, a novel power partial silicon-on-insulator (PSOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor is proposed with dual p- and n- charge accumulation (CA) layers near the source and the drain (DCAL-PSOI). Two new high electric field peaks are introduced by the two p- and n- CA layers in the proposed structure. Hence, a more uniform electric field is obtained due to modulation of the electric field in the drift region by the charges located in the p- and n- CA layers and buried oxide surface. Therefore, the vertical breakdown voltage (BV) is significantly improved by reducing the high bulk electric field around the source and drain regions. The influences of the proposed structure parameters on device characteristics are analyzed. For the DCAL-PSOI LDMOS with a 120-μm drift region length, the maximum BV of 1317 V is obtained by the simulation, while at the same drift region length, the maximum BVs of the conventional PSOI (C-PSOI) and conventional silicon-on-insulator (C-SOI) devices are 628 and 330 V, respectively. Moreover, the device exhibits a superior specific on-resistance (Ron, sp) of 0.34 Ω·cm2, which shows that the on-resistance of the optimized DCAL-PSOI are decreased by 91%-95% in comparison to the C-PSOI. The superior BV and Ron, sp yield to a power figure of merit (BV2/Ron, sp) of 5.1 MW/cm2. Also, the Si window alleviates the self-heating effect, and the maximum temperature of the proposed structure reduces as compared with the C-PSOI and C-SOI devices.
Keywords :
MOSFET; electric breakdown; silicon-on-insulator; C-PSOI devices; C-SOI devices; dual p- and n- charge accumulation layer; high electric field; lateral double-diffused metal-oxide-semiconductor field-effect transistor; partial SOI LDMOSFET; power figure of merit; power partial silicon-on-insulator; self-heating effect; size 120 nm; vertical breakdown voltage; voltage 1300 V; voltage 1317 V; voltage 330 V; voltage 628 V; Doping; Epitaxial layers; FETs; Fabrication; Helium; Power integrated circuits; Silicon on insulator technology; Substrates; Temperature; Voltage; Breakdown voltage (BV); charge accumulation (CA) layer; electric field; lateral double-diffused metal–oxide–semiconductor field-effect transistor (LDMOSFET); partial silicon-on-insulator (PSOI); self-heating effect (SHE); specific on-resistance $(R_{{rm on}, {rm sp}})$ ;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
Conference_Location :
6/1/2010 12:00:00 AM
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2010.2050100
Filename :
5475312
Link To Document :
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