A Novel Time Domain Method to Extract Equivalent Circuit Model of Patterned Ground Structures

A novel and efficient time-domain method is proposed to extract the RLC equivalent circuit model of the patterned ground structure. Based on time domain reflection analysis and Laplace transform, two analytical equations are derived to compute the corresponding L and C values. The non-ideal effect of the excitation source and nonzero rising time in time domain reflectometry (TDR) measurement and analysis is also considered. The equivalent R due to the conductor loss of the slot is obtained by the steady state DC level in TDR waveform. Two test samples are fabricated on a Duroid substrate and a FR4 board to verify the accuracy of the extracting method. The extracted RLC models for these two cases have a good agreement with the full-wave simulation and measurement results both in the time domain and frequency domain.