Title :
A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications
Author :
Yen, Shao-Wei ; Hung, Shiang-Yu ; Chen, Chih-Lung ; Chang, Hsie-Chia ; Jou, Shyh-Jye ; Lee, Chen-Yi
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
An LDPC codec chip supporting four code rates of IEEE 802.15.3c applications is presented. After utilizing row-based layered scheduling, the normalized min-sum (NMS) algorithm can reduce half of the iteration number while maintaining similar performance. According to the unique code structure of the parity-check matrix, a reconfigurable 8/16/32-input sorter is designed to deal with LDPC codes in four different code rates. Both sorter input reallocation and pre-coded routing switch are proposed to alleviate routing complexity, leading to 64% input reduction of multiplexers. In addition, an adder-accumulator-shift register (AASR) circuit is proposed for the LDPC encoder to reduce hardware complexity. After implemented in 65-nm 1P10M CMOS process, the proposed LDPC decoder chip can achieve maximum 5.79-Gb/s throughput with the hardware efficiency of 3.7 Gb/s/mm2 and energy efficiency of 62.4 pJ/b, respectively.
Keywords :
CMOS logic circuits; adders; codecs; parity check codes; personal area networks; shift registers; CMOS process; IEEE 802.15.3c application; adder accumulator shift register circuit; bit rate 5.79 Gbit/s; code structure; energy efficient multirate LDPC codec chip; input sorter; iteration number; normalized min-sum algorithm; parity check matrix; precoded routing switch; row based layered scheduling; size 65 nm; sorter input reallocation; Decoding; Hardware; IEEE 802.15 Standards; Logic gates; Parity check codes; Registers; Scheduling; IEEE 802.15.3c; low-density parity-check (LDPC) codes; row-based layered scheduling;
Journal_Title :
Solid-State Circuits, IEEE Journal of
Conference_Location :
5/10/2012 12:00:00 AM
DOI :
10.1109/JSSC.2012.2194176
