A Lossless Data Compression System for a Real-Time Application in HEP Data Acquisition

This paper presents a compression system optimized for the reduction of data from pulse digitizing electronics. Such systems are widely used in High Energy Physics experiments for the collection of signals from calorimeters, Time Projection Chambers and in general all detectors that produce a signal amplified and/or shaped to a linear pulse. The Time Projection Chamber of the ALICE experiment will be used as an illustration of our method, which we believe is widely adaptable to other data acquisition chains in High Energy Physics. To go beyond what can be achieved by conventional lossless compression schemes, which are ultimately limited by the intrinsic entropy of the incoming data, the proposed compression method makes use of a new scheme where instead of handling the data from the ADC as individual uncorrelated samples, an entire vector of samples is compressed. Our method works by first approximating the incoming vectors formed by the digitization of the shaped pulses with a set of digitized reference vectors stored in a memory and retaining only the differences between these vectors using Huffman compression. In standard data compression language, this corresponds to a vector quantization combined with Huffman coding. The performance of the described compression method was first evaluated by modeling the algorithm in Matlab using input data measured from the TPC in the ALICE experiment. A compression of 49% has been achieved. It has to be noted that the entropy computed on these same 10 bit original data was only 6.2 bit/symbol thus allowing a maximum compression factor of 38% only. The compression method was subsequently modeled in Verilog and synthesized to be combined with the other logic in the actual Read-out Control Unit of the ALICE TPC. First tests with actual hardware were performed using a Virtex-4 development board running at 80 MHz. The results showing the efficiency of the implementation using cosmic ray data are presented. The algorithm is execute- - d in this hardware with a latency of around 24 clock cycles at 40 MHz and takes about 2000 logic slices to be implemented.