Title :
Ultra-area-efficient three-stage amplifier using current buffer Miller compensation and parallel compensation
Author :
Yan, Zhennan ; Mak, Pui-In ; Law, Man-Kay ; Martins, Rui P.
Author_Institution :
State-Key Lab. of Analog & Mixed-Signal VLSI, Univ. of Macau, Macao, China
Abstract :
An ultra-compact three-stage amplifier is proposed by merging current buffer Miller compensation with parallel compensation, which achieves significant improvement in area efficiency without sacrificing the gain-bandwidth product (GBW) and power. Fabricated in 0.35 m CMOS the amplifier measures 4.98 MHz GBW at 150 pF load while drawing 20 A at 2 V. The entailed compensation capacitance is minimised to 1.5 pF and the chip size is merely 0.012 mm2.
Keywords :
CMOS analogue integrated circuits; amplifiers; compensation; CMOS; GBW; capacitance 1.5 pF; capacitance 150 pF; compensation capacitance; current 20 A; current buffer Miller compensation; gain-bandwidth product; parallel compensation; size 0.35 m; ultraarea-efficient three-stage amplifier; ultracompact three-stage amplifier; voltage 2 V;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2012.0711
