ASIC design for cell search in 3GPP W-CDMA

This paper deals with an ASIC design and realization for a pipelined cell search algorithm in the 3GPP W-CDMA system. Pipelining three stages of cell search provides preferable performance, but also results in greed for high computing power. The ASIC implementation furnishes this computing power demand with a high-performance, cost-effective, and low-power solution. In the ASIC design, two synchronization code matched correlators are well designed and realized with reduced computing power. A weighted comma-free Reed-Solomon decoder is also proposed with superior performance, and realized in a cost-effective and low-power architecture. Finally, the cell search chip is designed in a 3.3-V 0.35-μm CMOS technology with 4×4-mm² core area and 1.32 W power dissipation, complying with the 3GPP W-CDMA system specifications