Title :
A robust handshake for asynchronous system
Author :
Cheng, Kuo-Hsing ; Chang, Wei-Chun ; Tu, Chia-Ming
Author_Institution :
Dept. of Electr. Eng., Tam-Kang Univ., Tam-Shei, Taiwan
Abstract :
In this paper, a new handshake methodology to enhance the performance of the asynchronous systems is proposed. The proposed handshake methodology has more flexibility to design an asymmetric asynchronous system. The proposed handshake methodology also has some advantages, like latch free, robust, high throughput, very short pre-charge time, less transistors, and more flexibility in asymmetry data path. A technique that combines a single-rail dynamic circuit with a dual-rail dynamic circuit was proposed and used to design in the data path. In the critical delay data paths, the dual-rail dynamic circuits were used to improve the operating speed. In others the single-rail dynamic circuits were used. It brings some advantages that reduce power consumption and die area while maintaining the calculation speed. Finally, an asynchronous array multiplier was designed and implemented by the new robust handshake methodology. Based on the TSMC 0.35 μm CMOS technology, the simulation result of the maximum throughput is about 2.5 ns.
Keywords :
CMOS logic circuits; asynchronous circuits; integrated circuit design; multiplying circuits; 0.35 micron; 2.5 ns; TSMC 0.35 μm CMOS technology; asymmetric system; asymmetry data path; asynchronous array multiplier; asynchronous system; calculation speed; critical delay data path; dual-rail dynamic circuit; handshake methodology; high throughput; latch free; operating speed; robust circuit; robust handshake; short pre-charge time; single-rail dynamic circuit; CMOS technology; Clocks; Detectors; Energy consumption; Logic circuits; MOS devices; Quadratic programming; Robustness; Throughput; Voltage;
Conference_Titel :
System-on-Chip for Real-Time Applications, 2003. Proceedings. The 3rd IEEE International Workshop on
Print_ISBN :
0-7695-1944-X
DOI :
10.1109/IWSOC.2003.1212998