An efficient, high speed architecture for JPEG2000 MQ-coder

JPEG is the most commonly used image compression standard in today´s world. Researchers have found that JPEG has many limitations, in order to overcome all those limitations and to add on new improved features, ISO and ITU-T have come up with new image compression standard, which is JPEG2000. The JPEG2000 is intended to provide a new image coding/decoding system using state of the art compression techniques, based on the use of two important parts coding/decoding processes which are Wavelet Transform and Arithmetic Coding. As it´s hard to meet the real-time requirement of image compression systems by software, it is necessary to implement compression system by hardware. The embedded block coding with optimized truncation (EBCOT) algorithm is the heart of the JPEG 2000 image compression system. Context Based Adaptive Arithmetic coding is used and the MQ coder is adopted in the JPEG2000. In this paper we propose efficient faster architecture for the JPEG2000 MQ-Coder which is implemented in VHDL hardware description language and synthesized using Xilinx´s design flows ISE 13.1. The implementation results show that the design operates at 354.937 MHz when implemented on Virtex-6. Post synthesis simulations indicate that the proposed architecture is able to compress 35 video frames/s of high definition TV of 1920p.