Area efficient, high speed VLSI design for BPC coder in JPEG 2000

JPEG 2000 is an international standard for still images intended to overcome the shortcomings of the existing JPEG standard. Compared to JPEG image compression techniques, JPEG 2000 standard has not only better compression ratios, but it also offers some exciting features. As it´s hard to meet the real-time requirement of image compression systems by software, it is necessary to implement compression system by hardware. In this paper we proposed an optimized architecture of bit plane coder for Embedded Block Coding with Optimal Truncation (EBCOT) algorithm. The proposed design is implemented on an FPGA platform. EBCOT is very important in the compression process of the JPEG 2000 standard. The proposed architecture is on four coding operations which are pipelined. The proposed architecture is implemented in a causal mode.