Reduction of operating voltage in organic transistor and CMOS circuit utilizing high-k dielectric

Employment of high-k dielectric is one of the most important strategies to reduce operating voltage of an integrated circuit. This paper demonstrates experiments on organic FET and CMOS circuit where the dielectric layer was constructed of P(VDF-TrFE) and PS polymer dielectric. The dielectric constant of compound dielectric increased about three times in comparison with that of pristine PS. This contributes into lowering the operating voltage transistor circuit. The experimental results indicated that high-k dielectric of P(VDF-TrFE) and PS may be suitable for flexible low-power organic electronics.