A Novel SRAM Cell Design Using Reversible Logic

With the advancement in technology and type of usage of the electronics devices in different applications, demands huge size memories to store or process the data. Typically Static Random Access Memory (SRAM) cells are used due to its high speed access characteristics. With the exponential increase in the size of the memory, the power consumed by the memory cells are also increasing exponentially. Reversible circuits in recent years have gained its interest due to its low power characteristics. This paper proposes a novel SRAM cell design using reversible logic. The proposed design minimizes the number of garbage outputs by 66.66%, Quantum cost by 71.5% and Quantum delay by 68.5% than the existing designs. This paper also elaborates the implementation details of 16 × 8 SRAM array with minimum garbage and quantum cost.