DocumentCode :
3563975
Title :
Effects of channel barrier layer on the analog performance of p-Ge/ n-InGaAs CMOS devices
Author :
Tewari, Suchismita ; Biswas, Abhijit ; Mallik, Abhijit
Author_Institution :
Inst. of Radio Phys. & Electron., Univ. of Calcutta, Kolkata, India
fYear :
2014
Firstpage :
1
Lastpage :
4
Abstract :
MOSFETs based on high mobility channel materials such as Ge for p-MOS devices and InGaAs for n-MOS devices have shown promise for future nanoelectronics. Mobility of carriers can further be improved with the incorporation of barrier layer on top of the channel. We report the impact of barrier layer on the analog performance of hybrid CMOS comprising Ge channel p-MOSFET and InGaAs channel n-MOSFET. Our findings show that the InP barrier thickness of 0.7 nm for InGaAs n-MOSFET and the 0.5 nm thick Si barrier in Ge p-MOSFET exhibit strongest carrier confinement within the respective channel. The gain of hybrid CMOS using such barrier thickness exhibits improvement of 150% and 110% at channel length Lg= 30 nm and 20 nm, respectively. Furthermore, our studies reveal that 89.7% and 83% improvement of gain bandwidth product of hybrid CMOS using such barrier thickness at Lg= 30 nm and 20 nm, respectively are observed compared with equivalent Si CMOSFETs.
Keywords :
CMOS integrated circuits; III-V semiconductors; MOSFET; carrier mobility; elemental semiconductors; gallium arsenide; germanium; indium compounds; CMOS device; Ge-InGaAs; MOSFET; analog performance; carrier confinement; channel barrier layer effect; distance 20 nm; distance 30 nm; high mobility channel material; nanoelectronics; size 0.5 nm; size 0.7 nm; CMOS integrated circuits; Indium gallium arsenide; Indium phosphide; MOSFET; MOSFET circuits; Silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Emerging Technology Trends in Electronics, Communication and Networking (ET2ECN), 2014 2nd International Conference on
Print_ISBN :
978-1-4799-6985-2
Type :
conf
DOI :
10.1109/ET2ECN.2014.7044938
Filename :
7044938
Link To Document :
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