FPGA implementation of multipliers for ECC

Author

Kodali, Ravi Kishore ; Gomatam, Prasanth ; Boppana, Lakshmi

Author_Institution

Dept. of Electron. & Commun. Eng., Nat. Inst. of Technol., Warangal, India

fYear

2014

Firstpage

1

Lastpage

5

Abstract

Scalar Multiplication(SM) is the most frequently used operation in Elliptic Curve Cryptography(ECC). The efficiency of an ECC based system depends on the efficient implementation of SM. The type of basis used while designing a cryptosystem determines the space and time complexities. We implemented two multipliers based on Optimal Normal Basis of type II(ONB) and polynomial basis. This work uses Karatsuba and Sunar-Koc algorithms. The hardware implementations of both the multipliers have been carried out for different key lengths: 243, 251, and 270 bits. The FPGA device used for hardware implementation is XC6VLX240T(Virtex-6). The synthesis results are compared qualitatively in terms of hardware complexities for these key lengths.

Keywords

computational complexity; field programmable gate arrays; public key cryptography; ECC based system; FPGA implementation; Karatsuba algorithms; ONB; Sunar-Koc algorithms; XC6VLX240T; elliptic curve cryptography; optimal normal basis; polynomial basis; scalar multiplication; space complexities; time complexities; Computers; Elliptic curve cryptography; Hardware; Polynomials; Time complexity; ECC; Karatsuba multiplier; Sunar-Koc multiplier;

fLanguage

English

Publisher

ieee

Conference_Titel

Emerging Technology Trends in Electronics, Communication and Networking (ET2ECN), 2014 2nd International Conference on

Print_ISBN

978-1-4799-6985-2

Type

conf

DOI

10.1109/ET2ECN.2014.7044939

Filename

7044939