Title :
Design of sample and hold for 16 bit 5 Ms/S pipeline analog to digital converter
Author :
Mohapatra, Satyajit ; Gupta, Hari Shanker ; Mohapatra, Nihar R. ; Mehta, Sanjeev ; Chowdhury, Arup Roy
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Ahmedabad, Ahmedabad, India
Abstract :
This work presents the design and simulation of a low power CMOS Sample and Hold OTA for a 16bit, 5Ms/S pipelined ADC. The designing of high precision amplifiers is challenging in modern CMOS process. It drives ADC design methodology towards advance calibration approaches and compromised with low SNR. This paper deals with advance design techniques for High gain like triple cascode and achieves a DC gain of 132 dB and 68 MHz unity gain bandwidth with a phase margin of 88 degrees while driving the 16pf load of the first stage. Transient response of Charge Redistribution SHA shows settling accuracy of 15uV in 66 nanoseconds while consuming 20mW power. Switched capacitor CMFB has been implemented for the gain boosting amplifiers and main stage amplifier respectively. The design has been implemented in UMC 0.18μm technology. Design methodology for high gain and better settling performance at low power are also discussed in detail.
Keywords :
analogue-digital conversion; calibration; low-power electronics; operational amplifiers; sample and hold circuits; transient response; ADC design methodology; SHA; UMC technology; bandwidth 68 MHz; calibration approaches; capacitance 16 pF; charge redistribution; gain 132 dB; gain boosting amplifiers; low power CMOS OTA; main stage amplifier; pipeline analog to digital converter; power 20 mW; sample and hold design; settling performance; size 0.18 mum; switched capacitor CMFB; time 66 ns; transient response; voltage 15 muV; word length 16 bit; Accuracy; Bandwidth; Boosting; Capacitors; Equations; Gain; Topology; CMOS Technology; Common Mode Feedback (CMFB); High Resolution; Multiplying Digital to Analog Converter (MDAC); Operational Transconductance Amplifier (OTA); Pipeline; Sample and Hold Amplifier (SHA); Settling Response;
Conference_Titel :
Emerging Technology Trends in Electronics, Communication and Networking (ET2ECN), 2014 2nd International Conference on
Print_ISBN :
978-1-4799-6985-2
DOI :
10.1109/ET2ECN.2014.7044952