A reconfigurable cache architecture

All cache ways in w-way set associative cache are enabled during operation. This paper proposes an architecture to enable the occupied ways of w-way set associative cache. A variable set cache architecture is assumed. The proposed model introduces sequential component in cache circuit to enable the selected ways. The ways are put in off mode initially. The proposed model is simulated with SPEC2K benchmarks. The proposed model shows average power saving of 6.7% for level one cache of 2048 sets with associativities 8, 16, 32, level two cache size of 4096 sets with associativities 16, 32, 64 respectively in two level inclusive cache. The proposed model shows average power improvement of 4.7% for level one cache of 4096 sets with associativities 8, 16, 32, level two cache of 8192 sets with associativities of 16, 32, 64 respectively. The average memory access time is comparable in all configurations with the traditional model.