Title :
Power efficient architecture for network intrusion detection system
Author :
Bontupalli, VenkataRamesh ; Hasan, Raqibul ; Taha, Tarek M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Dayton, Dayton, OH, USA
Abstract :
With the rise in cyber-attacks on computing systems and the rapid increase in use of mobile systems, it is essential to secure these mobile devices. Given that these systems can roam on multiple networks, with no guarantee on security adopted on each network, including Intrusion Detection Systems (IDS) on the mobile platforms can be beneficial in preventing cyber-attacks. One of the key problems with implementing IDS on mobile platforms is the increased power consumption. This paper presents low power circuits that implement the string matching tasks within the Snort IDS. These tasks can take up to 80% of the power consumed for Snort. The circuit presented is based on memristor crossbars and evaluate Snort rules at 0.013mW per signature. The circuits are easy to program, utilizing only two resistance states for the memristors. They are highly parallel and dense, utilizing a brute-force string matching algorithm. These circuits could additionally be utilized for other string matching operations.
Keywords :
memristor circuits; mobile computing; mobile handsets; power aware computing; security of data; string matching; IDS; Snort IDS; brute-force string matching algorithm; computing systems; cyber-attacks; memristor crossbars; mobile platforms; mobile systems; network intrusion detection system; power circuits; power consumption; power efficient architecture; string matching operations; Computer architecture; Intrusion detection; Inverters; Memristors; Mobile communication; Neurons; Pattern matching; Deep packet inspection; Snort; intrusion detection system; memristor crossbars; network security; string matching;
Conference_Titel :
Aerospace and Electronics Conference, NAECON 2014 - IEEE National
Print_ISBN :
978-1-4799-4690-7
DOI :
10.1109/NAECON.2014.7045811