A hierarchical traffic shaper for packet switches

This paper presents a hierarchical traffic shaper implementation which can support a large number of connections with a wide range of rates and burstiness without the loss of granularity in cells´ departure time. In the proposed scheme, through a combination of per-virtual-connection-queues along with two stages of timing queues, we can implement exact sorting with substantial reduced memory size. Through comparison with other existing architectures, we show that the new architecture reduces the implementation complexity greatly. From simulation experiments, we show that the architecture doesn´t introduce any sorting inaccuracy compared to other existing schemes. The proposed hierarchical traffic shaper implementation not only can manage buffer and bandwidth resources effectively in large, high-speed ATM switches, but also can be implemented efficiently with off the shelf hardware technology