Optimal Pipeline Performance via Transactional Slice with No Branch Prediction Overhead

One of decisive feature in computer system design is the assessment of instruction pipeline. To design it carefully with minimum complexity to achieve enhanced performance and optimum result could be a powerful method. In order to achieve pipeline throughput close to ideal, the penalties of different hazards must be reduced. Branches are also one of those decisive substances that degrade the efficiency and can have dominating effect on the overall performance of CPU pipeline. Transactional Slice (TS) is one of the optimal solutions to tackle this issue, where the last instruction is always branch. Experiments are conducted on SPEC cpu2006 benchmark using Intel´s pin tool to estimate the size of the transactional slice. Pipeline efficiency is evaluated in this paper in terms of timing and pipelining model. It is observed that the transactional slice mechanism optimizes the efficiency of instruction pipeline.