Analog circuit and device interaction in high-speed SerDes design in 16nm FinFET CMOS technology

SerDes deals with data serialization, deserialization and channel equalization up to data rate of 28+Gb/s. Process technology and device characteristic greatly impacts architecture, circuit topology, and design merit of a SerDes. Several architecture choices, analog circuits, and techniques to mitigate undesired device characteristic in 16nm FinFET are discussed in this paper. With advanced CMOS technology and mitigation techniques, a prototype 28Gb/s SerDes was developed and demonstrated desired performance, power and die area.