Title :
FDSOI CMOS devices featuring dual strained channel and thin BOX extendable to the 10nm node
Author :
Liu, Q. ; DeSalvo, B. ; Morin, P. ; Loubet, N. ; Pilorget, S. ; Chafik, F. ; Maitrejean, S. ; Augendre, E. ; Chanemougame, D. ; Guillaumet, S. ; Kothari, H. ; Allibert, F. ; Lherron, B. ; Liu, B. ; Escarabajal, Y. ; Cheng, K. ; Kuss, J. ; Wang, M. ; Jung,
Author_Institution :
Albany NanoTech, STMicroelectron., Albany, NY, USA
Abstract :
We report FDSOI devices with a 20nm gate length (LG) and 5nm spacer, featuring a 20% tensile strained Silicon-on-Insulator (sSOI) channel NFET and 35% [Ge] partially compressive strained SiGe-on-Insulator (SGOI) channel PFET. This work represents the first demonstration of strain reversal of sSOI by SiGe in short channel devices. At Vdd of 0.75V, competitive effective current (Ieff) reaches 550/340 μA/μm for NFET, at Ioff of 100/1 nA/μm, respectively. With a fully strained 30% SGOI channel on thin BOX (20nm) substrate and Vdd of 0.75V, PFET Ieff reaches 495/260 μA/μm, at Ioff of 100/1 nA/μm, respectively. Competitive sub-threshold slope and DIBL are reported. With the demonstrated advanced strain techniques and short channel performance, FDSOI devices can be extended for both high performance and low power applications to the 10nm node.
Keywords :
CMOS integrated circuits; Ge-Si alloys; elemental semiconductors; field effect transistors; silicon-on-insulator; FDSOI CMOS devices; advanced strain techniques; dual strained channel; short channel performance; size 20 nm; strain reversal; strained SiGe-on-insulator channel PFET; tensile strained silicon-on-insulator channel NFET; thin BOX; voltage 0.75 V; Electrostatics; Logic gates; Performance evaluation; Silicon; Silicon germanium; Strain; Substrates;
Conference_Titel :
Electron Devices Meeting (IEDM), 2014 IEEE International
DOI :
10.1109/IEDM.2014.7047014
