Title :
Experimental realization of complementary p- and n- tunnel FinFETs with subthreshold slopes of less than 60 mV/decade and very low (pA/μm) off-current on a Si CMOS platform
Author :
Morita, Y. ; Mori, T. ; Fukuda, K. ; Mizubayashi, W. ; Migita, S. ; Matsukawa, T. ; Endo, K. ; O´uchi, S. ; Liu, Y. ; Masahara, M. ; Ota, H.
Author_Institution :
Nat. Inst. of Adv. Ind. Sci. & Technol. (AIST), Tsukuba, Japan
Abstract :
Complementary (p- and n-type) tunnel FinFETs operating with subthreshold slopes (SSs) of less than 60 mV/decade and very low off-currents (on the order of a few pA/μm) have been experimentally realized on the Si CMOS platform. Improvements in the SSs have been realized by optimizing epitaxial channel growth on heavily arsenic- and boron-doped source surfaces for purging interface defects at the epitaxial tunnel junctions. By improving the interface quality, SSs of 58 and 56 mV/decade and on/off current ratios (ON/OFF) of 2 × 106 and 3 × 104 (with VD = |0.2| V) were respectively obtained for p- and n- tunnel FETs (TFETs) simultaneously.
Keywords :
CMOS integrated circuits; MOSFET; elemental semiconductors; epitaxial growth; silicon; CMOS platform; Si; arsenic-doped source surfaces; boron-doped source surfaces; complementary n- tunnel FinFET; complementary p-tunnel FinFET; epitaxial channel growth; epitaxial tunnel junctions; interface quality; subthreshold slopes; CMOS integrated circuits; Epitaxial growth; FinFETs; Silicon; Surface cleaning;
Conference_Titel :
Electron Devices Meeting (IEDM), 2014 IEEE International
DOI :
10.1109/IEDM.2014.7047020
